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10-13-2015
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Oct 13, 2015Last Visited
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| 2638 | 04-29-2015 11:27 AM |
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| Member Since | 01-17-2014 06:47 AM |
| Date Last Visited | 10-13-2015 04:17 PM |
| Posts | 2 |
04-29-2015
11:27 AM
Hi, I've been searching for documentation on the internal architecture for pa5000 series (pa5050 to be precise). I've not been able to find it however. I'm especially interested in how the fysical interfaces are connected what the throughput of the different asic's are (if there is any sort of over subscription). Can anyone help me? With Kind regards,
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