Interal Architecture of the fpga / asic for pa hardware models

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Interal Architecture of the fpga / asic for pa hardware models

L0 Member


I've been searching for documentation on the internal architecture for pa5000 series (pa5050 to be precise). I've not been able to find it however. I'm especially interested in how the fysical interfaces are connected what the throughput of the different asic's are (if there is any sort of over subscription). Can anyone help me?

With Kind regards,


L7 Applicator

PAN does not publish this type of information publicly.  Contact your Sales Engineer and you can see some of this with a NDA (non-disclosure agreement) with your company and PAN.

Steve Puluka BSEET - IP Architect - DQE Communications (Metro Ethernet/ISP)
ACE PanOS 6; ACE PanOS 7; ASE 3.0; PSE 7.0 Foundations & Associate in Platform; Cyber Security; Data Center
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