Interal Architecture of the fpga / asic for pa hardware models

[THVHPBelgacom]

Hi,

I've been searching for documentation on the internal architecture for pa5000 series (pa5050 to be precise). I've not been able to find it however. I'm especially interested in how the fysical interfaces are connected what the throughput of the different asic's are (if there is any sort of over subscription). Can anyone help me?

With Kind regards,

[pulukas]

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